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TB1305FG, TB1308FG
TOSHIBA BiCMOS Integrated Circuit Silicon Monolithic
TB1305FG,TB1308FG
Component SW, Sync Separation and H/V Frequency Counter IC for TVs
The TB1305FG and TB1308FG include a component SW block, a prefilter for AD conversion, sync separation and H/V format detectors for TV component video signals. The TB1305FG and TB1308FG contribute to reduction in the proportion of PCB occupied by LCR filters and to the simplification of designs on analog interfaces. 2 The TB1305FG and TB1308FG are equipped with an I CBUS interface through which various functions can be controlled.
P-QFP48-1014-0.80
Weight: 0.83 g (typ.)
Features
COMPONENT BLOCK Component video input: TB1305FG 2 channels, TB1308FG 3 channels; RGB available Component video output Gain switching: 0dB / +6dB Bandwidth filter: prefilter for ADC; 4.2 to 31MHz variable) SYNC SEPARATION BLOCK Supports 525/60i/60p, 625/50i/50p, 750/50p/60p, 1125/50i/60i/50p/60p, 1250/50i, VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60 HD/VD input: 2 channels; positive and negative input acceptable HD/VD output: positive and negative output selectable Masking pseudo-sync for copyguard signal OTHERS Line detector for D-pin (2 channels) Horizontal and vertical frequency counter Format detection circuit for input signal Automatic sync process switching mode
Lineup Part No. TB1305FG TB1308FG Number of component video inputs 2 3
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Block Diagram
IICBUS
LINE1 DET
VD2-IN HD2-IN ADDRESS SYNC-OUT VD-OUT HD-OUT H Vcc Y-OUT H GND Cb-OUT Vf0ADJ Cr-OUT NC (SYNC3-IN)
BIAS BIAS
IICBUS
LINE2 DET LINE3 DET SW DET
SYNC TIP /BIAS
Y2/G2-IN LINE2-2
BIAS
Cb2/B2-IN LINE3-2
POL POL
SYNC SW
H-C/D V-C/D FREQ COUNT DUMMY SYNC
V SEP
SYNC SW
BIAS
Cr2/R2-IN SW LINE2
H/V SEP BAND WIDTH
YCbCr SW
SYNC TIP CLAMP
SYNC1-IN NC LINE1-1
+6dB AMP MUTE
+6dB AMP MUTE
BAND WIDTH
YCbCr SW
SYNC TIP /BIAS
Y1/G1-IN LINE2-1
+6dB AMP MUTE
BAND WIDTH
YCbCr SW
BIAS
Cb1/B1-IN LINE3-1
SYNC TIP CLAMP
BIAS
Cr1/R1-IN
NOTE: Pins 38, 39, 41 and 43 are available for the TB1308FG only. The pins are NC for the TB1305FG. The TB1305FG and TB1308FG do not support weak signals, ghost signals or other non-standard signals. Some functional blocks, circuits or constants may be omitted or simplified in the block diagram for explanatory purposes.
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Pin Functions
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal
31
3.3V
VCC pin for the logical circuits. 22 DIG VCC Supply power through a resistor from pin 31 like the Application Circuit. This pin voltage is clipped to 3.3 V (typ.) by the internal regulator.
22
50 50
500
3.3 V (typ.)
33
20 31 33 46 44 DIG GND H VCC H GND C VCC C GND GND pin for the logical circuits. VCC pin for the sync circuits. Connect 5.0 V (typ.) GND pin for the sync circuits. VCC pin for the video circuits. Connect 5.0 V (typ.) GND pin for the video circuits. Y or G input pin. 5 14 39 Y1/G1-IN Y2/G2-IN Y3/G3-IN Input the signal via a clamp capacitor. The clamp system is selectable by CLAMP register. NOTE: Pin 39 is not available for the TB1305FG. It is an NC pin. Y or CVBS input pin. 47 Y-IN Input the Y or CVBS signal in NTSC, PAL or SECAM from an AV-SW via a clamp capacitor. The clamp system is selectable by CLAMP register. 1 3 10 12 43 41 Cr1/R1-IN Cb1/B1-IN Cr2/R2-IN Cb2/B2-IN Cr3/R3-IN Cb3/B3-IN Cb/Cr, Pb/Pr or B/R input pin. Input the signal via a capacitor. NOTE: Pins 41 and 43 are not available for the TB1305FG. They are NC pins.
1 3 10 12 (43) (41) 46
200 200

5.0 V (typ.) 5.0 V (typ.) Sync tip level: 2.1 V (typ.)
46
Bias level: 2.7 V (typ.) RGB/YCbCr/YPbPr signal amplitude: 0.7 Vp-p (without sync)
2.9V/1.5V
200
5 14 (39) 47
200
200
100k 12k 2.8V
Sync tip level: 2.1 V (typ.)
44
Bias level: 2.7 V (typ.) Y/CVBS signal's amplitude: 1.0 Vp-p (with sync)
2.7 V bias (typ.) RGB/YCbCr/YPbPr signal amplitude: 0.7 Vp-p (without sync)
44
100k 12k 2.8V
46
1.7 V bias (typ.)
5V
Chroma signal input pin. Input C signal from AV-SW via a capacitor. 45 C-IN When this pin's voltage is High, TEST mode for shipping is active. The pin voltage must be less than 3.6 V during operating.
45
200 30.2k
C
Prohibited 3.6V
1.7V (typ)
1.5V TEST
44
0V
Sync tip level: 1.75 V (typ.)
31
10k
8 16 38
SYNC1-IN SYNC2-IN SYNC3-IN
Composite SYNC input pin to separate into H- and V-SYNC. Input the signal via a resister and a clamp capacitor. NOTE: Pin 38 is not available for the TB1305FG. It is an NC pin.
1Vp-p
8 16 (38) 33
or
1Vp-p
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Pin No.
Pin Name HD input pin.
Function
Interface Circuit
Input Signal/Output Signal
24 26
HD1-IN HD2-IN
Input a separated horizontal sync signal (1.0 to 2.0 Vp-p) via a resister and a coupling capacitor. The polarity of the input signal is detected and its leading edge becomes a timing trigger. VD input pin.
22 23 24 25 26
1.45 V bias (typ.)
200
or
20
23 25
VD1-IN VD2-IN
Input a separated vertical sync signal (1.0 to 2.0 Vp-p) via a resister and a coupling capacitor. The polarity of the input signal is detected and its leading edge becomes a timing trigger.
20k
6 15
LINE1-1 LINE1-2
LINE1 (number of lines) detection pin.
2 6 11 15
150k
46
Connect LINE1 of D-pin.
DC
200
1k
2 11
LINE3-1 LINE3-2
LINE3 (aspect ratio) detection pin. Connect LINE3 of D-pin.
10k
Th1
Th2
20k
DC
44
4 13
LINE2-1 LINE2-2
LINE2 (i/p) detection pin. Connect LINE2 of D-pin.
4 9 13 48
150k 40k
46
DC
200
1k 10k
48 9
SW LINE1 SW LINE2
SW LINE detection pin. Connect SW LINE of D-pin.
44
DC
32
Y-OUT
Y, G or CVBS signal output pin.
46
34
Cb-OUT
Cb, Pb, B or C signal output pin.
32 34 36
100
AC: 0 dB or +6 dB (typ.)
36
Cr-OUT
Cr, Pr or R signal output pin.
44
3.4V(typ.)
28
SYNC-OUT
Separated composite sync output pin.
31
250
0.1V(typ.)
3.4V(typ.) 0.1V(typ.)
HD or VD output pin. 29 30 VD-OUT HD-OUT The polarity of the output is selectable by HV-POL register. The tailing edge of the VD-OUT has a jitter. Use the leading edge only.
3.3k
28 29 30
100
or
33
3.4V(typ.) 0.1V(typ.)
31 17 42
100 100 DAC TEST
17 42
DAC1 DAC2
1-bit DAC output pin. Open-collector pin.
DC
33
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Pin No. Pin Name Function Interface Circuit
31
500
Input Signal/Output Signal
Crystal connection pin. 21 XTAL Connect a 3.579545 MHz crystal for NTSC demodulation to generate internal clocks.
21
2.5k
33
46
200
35
Vf0ADJ
A filter pin to adjust bandwidth filter characteristics.
35
200
44
46
1k
40
BIAS FIL
A filter pin for internal bias circuits.
40
1k
800
44
31 22
18
SDA
SDA pin for I2CBUS.
18
5k 50 ACK
SDA
Th: 2.25V(typ.) Th: 1.50V(typ.)
H to L: 1.50 V (typ.) L to H: 2.25 V (typ.)
20
31 22
19
SCL
SCL pin for I2CBUS.
Th: 2.25V(typ.) Th: 1.50V(typ.)
19
5k
H to L: 1.50 V (typ.) L to H: 2.25 V (typ.)
20
46
20k 60k
27
ADDRESS
20k
Slave address switching pin. Connect to 5 V Vcc or GND. Or leave this pin open.
27
5 V Vcc: Open: GND:
44
DCH/DDH DAH/DBH D8H/D9H
1k 10k 40 Th1 Th2
These pins are not used. 7 37 NC Connect to GND. NOTE: Pins 38, 39, 41 and 43 of the TB1305FG are not used . Connect them to GND.
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BUS Control Map
Write Mode
SA 00 01 02 03 D7 MUTE f0 SW fc HALF HV-SEP VGA-SEP SYNC SW 1(PS MASK) A SYNC S MODE
Slave address: D8H
D6 FILPASS D5 HD WIDTH
/ DAH / DCH
D4 DAC2 D3 DAC1 BANDWIDTH HV FREQ CLAMP HV-POL VD PHS D2 YCbCr SW D1 D0 GAIN PRESET 00000000 00000000 00000000 00000000
NOTE: Set PS MASK = 1 (ON) for except "Sync on G" input. Remark: SA = Sub-Address.
Read Mode
D7 0 1 2 3 4
Slave address: D9H
D6 LINE1 D5 LINE2
/ DBH / DDH
D4 LINE3 H FORMAT D3 D2 SW LINE1 D1 SW LINE2 V FORMAT VERSION D0
HD-POL H FM2
VD-POL V FM2 H IN
V IN
V-SYNC-W V FREQ DET
H FREQ DET
: Undefined
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Bus Control Functions
Write Mode
Register Name MUTE Swtches mute mode. 0: NORMAL Switches the bandwidth limit filter. 0: ON (by-pass) Switches the width of HD-OUT. HD WIDTH 0: WIDE 1: NARROW WIDE (0) 1: OFF 1: Video mute Function Preset Value NORMAL (0) ON (0)
FILPASS
Remark: HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format owing to crosstalk from HD-OUT to video signals so that spike noises on video signals will occur. 1-bit DAC switching
DAC1,2
Output voltages of DAC1 (pin 17) and DAC2 (pin 42) are controlled. DAC1/2 are open-collector pins. 0: LOW (ON) 1: HIGH (OPEN)
LOW (0)
Switches the component video input and line input 00: Y1 / Cb1 / Cr1 / LINE1, 2, 3-1 (pins 1, 2, 3, 4, 5, 6) YCbCr SW 01: Y2 / Cb2 / Cr2 / LINE1, 2, 3-2 (pins 10, 11, 12, 13, 14, 15) 10: Y / C (pins 45, 47. Cr-out is muted.) 11: Y3 / Cb3 / Cr3 (pins 39, 41, 43) NOTE: The data (11) is not available for the TB1305FG. Switches the output gain. Gain of YCbCr output (pins 32, 34, 36) is controlled. GAIN 0: 0 dB 1: +6 dB 0 dB (0) Y1 / Cb1 / Cr1 (00)
Remark: GAIN = 0 (0 dB) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of +6 dB mode. f0 SW Switches the f0 of bandwidth limit filter 0: HIGH Switches the f0 of bandwidth limit filter BANDWIDTH 0000000: MIN (low) 1111111: MAX (high) Switches the frequency of bandwidth limit filters for Cb/Cr fc HALF The cutoff frequency of bandwidth limit filters for Cb/Cr is 1/2 to Y. 0: OFF (same for 3 outputs) 1: ON (1/2 fc for Cb/Cr) 1: LOW HIGH (0) MIN (0000000)
OFF (0)
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Register Name Switches sync input. Sync input to HD/VD-OUT and to SYNC-OUT is selected. HD OUT (pin 30) 000 001 010 SYNC SW 011 100 101 110 111 HD1 (pin 24) HD2 (pin 26) HD1 (pin 24) HD2 (pin 26) VD OUT (pin 29) SYNC1 (pin 8) SYNC2 (pin 16) SYNC3 (pin 38: TB1308FG only) Not available VD1 (pin 23) VD2 (pin 25) VD1 (pin 23) VD2 (pin 25) SYNC1 (pin 8) SYNC2 (pin 16) SYNC3 (pin 38 : TB1308FG only) SYNC3 (pin 38: TB1308FG only) SYNC1 (000) SYNC OUT (pin 28) Function Preset Value
NOTE: SYNC3 of the data 010, 110, 111 is not available for the TB1305FG. Input format setting Set the horizontal and vertical mode according to the format that is input. 0000: 15.625 kHz, 50 Hz (625i) 0010: 31.25 kHz, 50 Hz (625p) 0001: 15.75 kHz, 60 Hz (525i) 0011: 31.5 kHz, 60 Hz (525p, VGA@60Hz)
0100: 28.125 kHz, 50 Hz (1125/50i) 0101: 33.75 kHz, 60 Hz (1125/60i) HV FREQ 0110: 37.5 kHz, 50 Hz (750/50p) 1000: 31.25 kHz, 50 Hz (1250i) 1001: 37.9 kHz, 60 Hz (SVGA@60Hz) 1010: 64 kHz, 60 Hz (1125/60p, SXGA@60Hz) 1011: 75 kHz, 60 Hz (UXGA@60Hz) 1100: 56.25 kHz, 50 Hz (1125/50p) 1101 ~ 1111: Not available Switches the separation level. The H/V sync separation level to SYNC-IN (pins 8, 16, 38) is switched. HV-SEP 0: LOW 1: HIGH LOW (0) 0111: 45 kHz, 60 Hz (750/60p, XGA@60Hz) 15.625 kHz, 50 Hz (0000)
Remark: The separation level is changed according to the ratio of negative sync width per H period and the connected resistance. Switches the separation level. The H/V sync separation level to SYNC-IN (pins 8, 16, 38) is switched for PC signals. 0: Normal (component video) 1: VGA Normal (0)
VGA-SEP
Remark: The separation level is changed according to the ratio of negative sync width per H period and the connected resistance. Switches the mask mode for pseudo-sync. PS MASK Pseudo-syncs in lines are removed. 0: OFF (V-BLK period only) 1: ON (all lines) OFF (0)
NOTE: Set PS MASK = 1 (ON) for except "Sync on G".
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Register Name Automatic sync processing mode. Sync processing mode is changed in accordance with the results obtained by the internal format detection circuits. Format detection is performed for a SYNC or HD/VD signal selected by SYNC SW. The result of detection is returned to H, V FORMAT and H, V FM2. The HV FREQ setting is invalid when this mode is active. 0: OFF (manual switching mode by HV FREQ setting) 1: ON Switches sync output mode. This function sets the dummy HD/VD output mode when there is no input. The frequency of the dummy HD/VD output depends on the HV FREQ setting (when A-SYNC = OFF) or H, V FORMAT (when A-SYNC = ON). H, V IN shows whether there is no input or not. 0: OFF (No HD and free-run VD output (approx. 44 Hz), when there is no input. However, in 1250i mode, no HD and no VD output, when there is no input.) 1: ON (Dummy HD/VD output when there is no input) Switches Y clamping mode. CLAMP This function sets the clamping mode for pins 5, 14, 39. 0: SYNC TIP CLAMP 1: BIAS SYNC TIP (0) Function Preset Value
A-SYNC
OFF (0)
S MODE
OFF (00)
Switches the polarity of the HD/VD output. HV-POL This function sets the polarity of HD/VD OUT (pins 29, 30). 0: Positive 1: Negative
Positive (0)
Switches the phase of dummy VD output. VD PHS VD PHS compensates for delay time so that the dummy VD-OUT phase is the same as that form the separated V-sync. 0: No delay 1: 0.2 H delay (0.15 H delay for 1125/50p) No-delay (0)
Read Mode
Register Name Function LINE1 detection for D-pin (for the number of lines) LINE1 00: 525 (480) 01: 750 (720) 10: ---11: 1125 (1080)
Detects the voltage of LINE1 selected by YCbCr SW. 11 is returned when the pin is not connected. LINE2 detection for D-pin (for i/p) LINE2 0: Interlace 1: Progressive
Detects the voltage of LINE2 selected by YCbCr SW. 1 is returned when the pin is not connected. LINE3 detection for D-pin (for aspect ratio) LINE3 00: 4:3 01: 4:3 letter box 10: ---11: 16:9
Detects the voltage of LINE3 selected by YCbCr SW. 11 is returned when the pin is not connected. SW LINE1 SW LINE1 (pin 48) detection for D-pin 0: Connected 1: Not connected
SW LINE2
SW LINE1 (pin 9) detection for D-pin 0: Connected Polarity detection to HD-IN 1: Not connected
HD-POL
0: Positive
1: Negative
Detects the width from the HD-IN pin to determine whether it is negative or not. When the High level of the input HD-IN is wider than approx 14 s, HD-POL shows 1.
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Register Name Polarity detection to VD-IN VD-POL 0: Positive 1: Negative Function
Detects the width from the VD-IN pin to determine whether it is negative or not. When the High level of the input VD-IN is wider than approx 4.5 ms, VD-POL shows 1. Horizontal format detection 0000: 15.625/15.75kHz 0001: 28.125kHz 0100: 37.5/37.9kHz 1000 56.25kHz H FORMAT 0101: 45/48kHz 1001 ~ 1111: Undefined 0010: 31.25/31.5kHz 0110: 64kHz/67.5kHz 0011: 33.75kHz 0111: 75kHz
Detects a horizontal format (horizontal frequency). NOTE1: Format detection errors such as the following can occur when suppressed syncs are input. See NOTE3 in the function description on Automatic sync processing mode, too. 525i input 525p detected, 625i input 625p detected, 1125i input 1125p detected 525p/625p input No V-sync detected NOTE2: When 525i, 625i, 1125/50i or 1125/60i signal is input, H FORMAT data can be incorrect caused by the pseudo-syncs for copy guard or the equalizing pulses. Vertical format detection
V FORMAT
00: 50 Hz
01: 60 Hz
10 ~ 11: Undefined
Detects a vertical format (horizontal frequency) according to V FREQ DET data. Horizontal format detection 2 H FM2 0: Known 1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on H FORMAT data. NOTE: H FM2 may indicate Unknown, when 525p input with pseudo sync signal for copy guard is input. Vertical format detection 2
V FM2
0: Known
1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on V FORMAT data. H IN Input detection to horizontal syncs 0: No signal 1: Signal
V IN
Input detection to vertical syncs 0: No signal V-SYNC width detection 0: Wide 1: Narrow 1: Signal
V-SYNC-W
Detects V-SYNC width for detecting 1250i format. Under A-SYNC = 1 (ON), V-SYNC-W shows 1, when the VD width from the VD-IN pin is narrower than approx 69 s, or when the V-SYNC width from the SYNC-IN pin is narrower than approx 27 s. IC version identification 00: TB1305FG 01: TB1308FG 10: ---11: ----
VERSION
Counts the vertical frequency of an input selected by SYNC SW. 0000000: Over 3.5kHz 10100001111111: No signal V FREQ DET How to calculate a vertical frequency (Y): Convert data read from V FREQ DET into decimal value and call it X. Vertical frequency (Y) = 1 / (X x 2.8607 x 10-4) The error range of X is -1 to +1. Counts the horizontal frequency of an input selected by SYNC SW. 00000000: No signal H FREQ DET 11111111: Over 85kHz [Hz] 1001111: 44Hz or less
How to calculate a horizontal frequency (Y): Convert data read from H FREQ DET into decimal value and call it X. Horizontal frequency (Y) = 1 / (0.003 / X) The error range of X is -1 to +1. [Hz]
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Note 1: In determining the decision algorithms (detection range, detection times and so on) for H/V frequency detection, it is necessary to take into account both previously mentioned cautions and other factors such as signal conditions and I2CBUS data transmission in the course of prototype TV set evaluation. Note 2: The READ BUS flags indicate that a certain signal is detected at a given moment. However, the detection result will not be very reliable if only one flag is checked. To obtain accuracy, it is recommended that a judgment will be made on the basis of confirming several times and verifying agreement among the majority of flags read in a sequence and/or at the same time.
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Function Descriptions
Vertical sync separation for 1250i/50
When HV FREQ = 1000, the vertical sync separation for 1250i/50 is accomplished through the use of a special circuit. The phase of the VD-out (pin 29) depends on the H-SYNC timing shown in the figure below. There is no VD-out when there is no H-SYNC input. In the manual sync processing mode (A-SYNC = OFF), use READ BUS functions, V-SYNC-W and H, V FORMAT (or H, V FREQ DET) to detect 1250i/50. NOTE: The VD-OUT's tailing edge has a jitter. Use the leading edge only.
HD width
HD-OUT width is selectable by HD WIDTH, as below. HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format owing to crosstalk from HD-OUT to video signals so that spike noises on video signals will occur.
1125/60p signal SYNC-IN (Y-IN)
HD-OUT (HD WIDTH=1) 0.65us (typ) HD-OUT (HD WIDTH=0) 1.65us (typ)
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Automatic sync processing mode (A-SYNC)
Counted horizontal and vertical frequency data to input signal are returned to READ BUS functions, H, V FREQ DET. Also, the detected format is returned to H, V FORMAT and H, FM2 when the H/V frequencies are in internal defined ranges. Input detection results, which indicate whether there is an input or not, for H, V-SYNC or HD, VD are returned to H, V IN. In automatic sync processing mode (when A-SYNC = ON), the TB1305FG and TB1308FG operate as indicated in the following table according to these READ data. INPUT CONDITION Standard format Non-standard format H, V FORMAT status The format as input H, V FM2 status Known H, V IN status Signal HD, VD outputs The separated sync as input
The status indicates not The separated sync as the current condition Unknown Signal input but the last detected format. Dummy HD and VD, of Known: The status indicates not which the frequency the current condition The status indicates not No signal No input depends on the H, V but the last detected the current condition but FORMAT status the last detected format. format. NOTE 3: The following format detection errors can occur when suppressed syncs are input. 525i input 525p detected, 625i input 625p detected, 1125i input 1125p detected 525p/625p inputs In case of the 525p/625p sync amplitude become bigger from zero to its standard gradually, V-sync of the input is not detected even though the sync amplitude is got back to its standard amplitude. The V-sync separation performance to the suppressed sync input may be improved when VGA-SEP is set to 1 (VGA), though the H and V separation level are also changed. NOTE 4: We recommend recognizing a format by H/V FREQ DET rather than one by H/V FORMAT because H FORMAT and H FM2 can indicate an incorrect data for 525i, 625i, 525p, 1125/50i and 1125/60i caused by the pseudo-syncs for copy guard or the equalizing pulses. NOTE 5: Dummy HD and VD may become unstable while the mode is changing from one format to another. By the way, in A-SYNC = OFF and S-MODE = ON mode, dummy HD and VD are output according to HV FREQ setting when there is no input.
Manual sync processing mode (A-SYNC = OFF *NOTE6)
HV FREQ = 625p is required to separate H-SYNC and V-SYNC properly. Set HV FREQ = 625p to count H/V-SYNC for Manual sync processing mode. The following is an example of how to detect H/V frequency when A-SYNC=OFF. 1. Set HV FREQ = 625p(0010) and read data such as H, V FREQ DET. 2. Detect the H/V frequencies by microprocessor or similar means, depending on the data obtained. 3. Set HV FREQ and so on to the detected mode. 4. Continue to monitor the obtained data such as H, V FREQ DET. When any alteration is recognized, set HV FREQ = 625p(0010) and detect again. Decision algorithms (for detection range, detection times and so on) for H/V frequency detection should be determined taking into account the above-mentioned errors in measuring H/V frequencies and the other factors such as signal conditions and I2CBUS data transmission in the course of prototype TV set evaluation. NOTE 6: We recommend recognizing formats for 525i and 625i signals by another device such as a color-decoder, not by this product, because 525i and 625i signals include non-standard signals. However, if you use this product to recognize formats including the standard 525i and 625i, set "A-SYNC = ON". Otherwise, H/V FREQ DET and H/V FORMAT may indicate incorrect value and VD-OUT may lock irregularly for 525i and 625i signals. Refer to the "Application circuit 3 (system configuration)", too.
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Sync separation level
The sync separation level is changed according to the ratio of H-sync width to one line and the connected resistance. Typical sync separation levels for each format are as follows. Then, VGA-SEP=1 for VGA to UXGA. Format 625/50i 525/60i 625/50p 525/60p 1125/50i 1125/60i 750/50p 750/60p 1250/50i 1125/50p 1125/60p VGA/60 SVGA/60 XGA/60 SXGA/60 HV-SEP = 0 (LOW) R = 1.2 k R = 1.5 k R = 1.8 k 22 22 22 21 31 26 29 24 25 36 31 15 15 17 27 28 28 28 27 39 33 37 31 32 45 39 19 18 22 33 33 34 34 32 45 39 43 37 37 51 45 23 22 26 39 HV-SEP = 1 (HIGH) R = 1.2 k R = 1.5 k R = 1.8 k 24 24 25 24 40 34 37 32 32 45 39 16 16 19 30 32 31 31 30 49 43 46 40 41 54 49 21 20 24 37 37 37 38 36 54 50 52 47 47 58 55 25 24 28 43
Unit [%] ; where 286 mVp-p sync for 525/60i and 300 mVp-p sync for others For "Sync on G" signal, HD-OUT is not output during V-sync period because there is no H-sync during V-sync period. Furthermore, for Sync on G of XGA input, HD-OUT disappears during active video period caused by unexpected lock of the internal V-BLK. The format detection and sync separation performances are changed due to the separation level set by HV-SEP, VGA-SEP setting and/or the connected resistance with SYNC-IN pin. The careful evaluations are required to set the separation level under consideration of expected input conditions such as a suppressed sync input, an input with V-sag and APL (Average Picture Level) fluctuations.
Note on Sync input pin
If the AC-coupling circuit is put before the SYNC-IN pin, the picture on the screen may be not stable. This is because the sync separation circuit is unable to follow the DC level fluctuation caused by APL (Average Picture Level) change in the input signal, and the HD and/or VD output is unable to synchronize the input. It is recommended to input signals via the DC-coupling buffer if necessary.
For the DC level fluctuation caused by APL change, the sync separation ability may be improved to change the setting of HV-SEP, VGA-SEP and/or changing the resister R. Furthermore, adding a high-resistance around several M between SYNC-IN pin and GND (or Vcc) may improve the sync separation ability. Adding DC restoration circuit such as a clamp circuit can be also effective for the improvement of DC level fluctuation. Also, refer to Sync separation level descriptions.
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Prefilter for AD converter
The filter of the TB1305FG and TB1308FG can be used as a prefilter for AD converter. The cutoff frequency is controllable by I2CBUS functions, FILPASS, f0-SW, BANDWIDTH and fc HALF. The characteristics for cutoff frequency and delay time are as below.
10 0 -10 Gain [dB] -20 -30 -40 -50 1.E+04 10k f0 f0 f0 f0 SW SW SW SW = Low, BANDWIDTH = min, fc HALF = ON = Low, BANDWIDTH = min = High, BANDWIDTH = min = High, BANDWIDTH = max 1.E+05 100k 1.E+06 1M Frequency [Hz] 1.E+07 10M 1.E+08 100M
Figure. Typical prefilter frequency characteristics
35 Cutoff frequency (-3 dB point) [MHz] 30 25 20 15 10 5 0 0 20 40 60 80 100 120 BANDWIDTH data [Dec] f0 f0 f0 f0 SW SW SW SW = = = = Low, fc HALF = ON High, fc HALF = ON Low High
Figure. Typical cutoff frequency (-3 dB point) characteristics of prefilter due to BANDWIDTH data.
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TB1305FG, TB1308FG
200 180 160 140 Delay time [ns] 120 100 80 60 40 20 0 0 20 40 60 80 100 120 BANDWIDTH data [Dec] f0 SW = Low, fc HALF = ON f0 SW = High, fc HALF = ON f0 SW = Low f0 SW = High
Figure. Typical delay-time (group delay @ 1MHz) characteristics of prefilter due to BANDWIDTH data.
Note on 1125/50p/60p input
When 1125/50p and/or 60p signal are input, GAIN = 0(0dB) and FILPASS = 0(ON) are recommended due to the performance of the slew rate and cutoff frequency of the TB1305FG and TB1308FG circuits. A gain amplifier and/or a prefilter for 1125/50p/60p should be added as external circuits, if necessary.
Note on video output pins
To conduct the video signal from the TB1305FG or TB1308FG to the following circuits, a buffer such as the one in the application circuits is required due to the drive capability of the TB1305FG and TB1308FG being insufficient, especially for high-frequency components. The DC levels of the video output vary according to I2CBUS functions, the APL of the input and temperature drift.Therefore, the DC levels should be re-clamped in connected circuits such as AD converters.
Recommended crystal oscillator
When a connected crystal oscillator is used for the XO, the following oscillation specifications are required. Oscillation frequency (fundamental): 3.579545 MHz (for NTSC decoding) Frequency tolerance: +/- 50 ppm
External CW input into crystal oscillator pin
Instead of connecting a crystal oscillator, it is possible to input an external CW (Continual Wave) into pin 21 through a capacitor as below. The specifications required for CW input are as follows. Input frequency (fundamental): 3.579545 MHz +/- 50 ppm Input amplitude: 1.0 Vp-p +/- 0.5 Vp-p
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TB1305FG, TB1308FG
How to deal with unused pins
Unused pins should be dealt with as below. Pins not mentioned below should be connected properly.
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 23 24 Pin Name Cr1/R1-IN LINE3-1 Cb1/B1-IN LINE2-1 Y1/G1-IN LINE1-1 NC SYNC1-IN SW LINE2 Cr2/R2-IN LINE3-2 Cb2/B2-IN LINE2-2 Y2/G2-IN LINE1-2 SYNC2-IN DAC1 VD1-IN HD1-IN
Procedure Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 2 Procedure 3 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 3 Procedure 3 Procedure 4 Procedure 4
Pin No. 25 26 27 28 29 30 32 34 36 37 38 39 41 42 43 45 47 48
Pin Name VD2-IN HD2-IN ADDRESS SYNC-OUT VD-OUT HD-OUT Y-OUT Cb-OUT Cr-OUT NC SYNC3-IN Y3/G3-IN Cb3/B3-IN DAC2 Cr3/R3-IN C-IN Y-IN SW LINE1
Procedure Procedure 4 Procedure 4 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 2 Procedure 3 Procedure 1 Procedure 1 Procedure 3 Procedure 1 Procedure 1 Procedure 1 Procedure 2
Procedure 1: Connect a 1 F capacitor between this pin and GND. Procedure 2: Connect to GND. Procedure 3: Leave open. Procedure 4: Connect a 10 k resister between this pin and GND.
NOTE: Pins 38, 39, 41 and 43 are NC pins for the TB1305FG. Of these, any unused pins should be dealt with as in "Procedure 2".
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TB1305FG, TB1308FG
How to Start the I CBUS
How to send bus data after power on is described below. Use software to handle the procedure. 1. Turn power on. 2. Transmit all write data.
2
How to Transmit/Receive via the I CBUS
Slave Address: Can Be Changed Using Pin 27.
Pin 27-GND: D8H/D9H
A6 1 A5 1 A4 0 A3 1 A2 1 A1 0 A0 0 W/R 0/1
2
Pin 27-OPEN: DAH/DBH
A6 1 A5 1 A4 0 A3 1 A2 1 A1 0 A0 1 W/R 0/1
Pin 27-Vcc: DCH/DDH
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 W/R 0/1
Start and Stop Conditions
SDA
SCL S Start condition P Stop condition
Bit Transmission
SDA
SCL SDA must not be changed SDA may be changed
Acknowledgement
SDA from transmitter SDA from receiver
High impedance at bit 9
Low impedance at bit 9 only 1 S Clock pulse for acknowledgement 8 9
SCL from master
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TB1305FG, TB1308FG
Data Transmit Format 1
S Slave address 7-bit 0A Sub address 8-bit A Transmit data 8-bit MSB P: End condition AP
MSB S: Start condition
MSB A: Acknowledgement
Data Transmit Format 2
S Slave address 0A Sub address A Transmit data 1 A A AP
Sub address
Transmit data n
Data Receive Format
S Slave address 7-bit MSB 1A Receive data 1 8-bit MSB Receive data n MSB AP
To receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. The slave receiver changes to a transmitter. The end condition is always created by the master.
Optional Data Transmit Format (Automatic Increment Mode)
S Slave address 7-bit MSB 0A1 MSB Sub address 7-bit A Transmit data 1 8-bit MSB Transmit data n 8-bit MSB AP
In this way, sub-addresses are automatically incremented from the specified sub-address and data are set.
I2CBUS Conditions
Parameter Low level input voltage High level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage at 3 mA sink current Input current each I/O pin with an input voltage between 0.1 VDD and 0.9 VDD Capacitance for each I/O pin SCL clock frequency Hold time START condition Low period of SCL clock High period of SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition Symbol VIL VIH Vhys VOL1 Ii Ci fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Min. 0 2.8 - 0 -10 - 0 0.6 1.3 0.6 0.6 50 100 0.6 1.3 Typ. - - 0.7 - - - - - - - - - - - - Max. 1.1 H-Vcc - 0.6 10 10 400 - - - - - - - - Unit V V V V A pF kHz s s s s ns ns s s
NOTE: This parameter is not tested during production and is provided only as information to assist the design of applications.
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TB1305FG, TB1308FG
Absolute Maximum Ratings (Ta = 25C)
Characteristic Supply voltage Input pin voltage Y or Sync input amplitude (pins 5, 8, 14, 16, 38, 39, 47) (Pins 38, 39 are for the TB1308FG only.) Power dissipation Power dissipation reduction rate Operating temperature Storage temperature Symbol VCCmax Vin Yin PD(Note 5) 1/ja Topr Tstg Rating 6.0 GND - 0.3 ~ Vcc + 0.3 2.0 1136 9.1 -20 ~ 75 -55 ~ 150 Unit V V Vp-p mW mW/C C C
Note 5: Refer to the figure below.
1136
Power consumption reduction ratio PD (mW)
682
0 0
25
75
150
Ambient temperature
Ta
(C)
Figure. PD - Ta Curve
Note 6: Handle pins 7 and 37 of the TB1305FG and TB1308FG with special care. These ICs are sensitive to electrostatic discharge and surge impulse.
Install the product correctly. Otherwise, it may result in break down, damage and/or degradation to the product or equipment. The absolute maximum ratings of a semiconductor device are a set of specified parameter values that must not be exceeded during operation, even for an instant. If any of these ratings are exceeded during operation, the electrical characteristics of the device may be irreparably altered, in which case the reliability and lifetime of the device can no longer be guaranteed. Moreover, operations with exceeded ratings may cause breakdown, damage and/or degradation in other equipment. Applications using the device should be designed so that no maximum rating will ever be exceeded under any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in these documents.
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TB1305FG, TB1308FG
Operating conditions
Characteristic Supply voltage (VCC) Y signal input amplitude G signal input amplitude Y signal input frequency Chroma signal input amplitude DC voltage of chroma input pin Cb, Cr, Pb, Pr signal input amplitude Cb, Cr, Pb, Pr signal input frequency R, G, B signal input amplitude R, G, B signal input frequency HD, VD signal input amplitude HD input frequency VD input frequency Pins 31, 46 Pin 22; supply power from H Vcc (pin 31) via a resistor. Pins 5, 8, 14, 16, 38, 39, 47; with sync Pins 8, 16, 38; with sync Pins 5, 14, 39 Pin 47 Pin 45 Pin 45 Pins 1, 3, 10, 12, 41, 43; 100% color bar signal Pins 1, 3, 10, 12, 41, 43 Pins 1, 3, 5, 10, 12, 14, 39, 41, 43; 100% white signal without sync Pins 1, 3, 5, 10, 12, 14, 39, 41, 43, 39, 41, 43 Pins 23, 24, 25, 26 Pins 24, 26 for freq counter Pins 23, 25 for freq counter H LINE1,3 LINE detection input voltage Pins 2, 6, 11, 15 M L LINE2 Pins 4, 13 H L H L 88/89H ADDRESS switching voltage Pin 27 DA/DBH DC/DDH SDA input current Pin 18 3.5 Description Min. 4.7 3.1 0 0 0 0 1.0 0 44 3.5 1.4 1.4 1.4 Typ. 5.0 3.3 1.0 1.0 0.3 0.7 0.7 5.0 2.2 GND 2.2 GND 5.0 GND GND Pin open C-Vcc C-Vcc 3 mA Max. 5.3 3.5 60 8 2 3.6 60 60 2.0 85 3500 C-Vcc 2.4 0.6 C-Vcc 0.6 C-Vcc 0.6 0.6 V V V Unit V Vp-p Vp-p MHz Vp-p V Vp-p MHz Vp-p MHz Vp-p kHz Hz
SW LINE
Pins 9, 48
V
Remark: Supply power to all Vcc pins (pins 22, 31 and 46). NOTE: Pins 38, 39, 41 and 43, as Y/Cb/Cr/SYNC3-IN, are available for the TB1308FG only. Pins 38, 39, 41 and 43 of the TB1305FG are NC pins.
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Electrical Characteristics
Current Consumption
Pin Name C VCC (pin 46) H VCC (pin 31) D VCC (pin 22) Symbol ICCC ICCH ICCD Test Conditions Resistance to 5 V; R = 150 Min 30.0 4.5 8.5 Typ. 38.0 6.0 10.5 Max 46.0 7.5 12.5 mA Unit
(Unless otherwise specified, C and H VCC = 5 V, D VCC = 3.3 V, Ta = 25C, I2CBUS data: preset values)
Pin Voltage (test condition: no signal input)
Pin No. 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27 32 34 35 36 38 39 40 41 43 45 47 48 Pin Name Cr1/R1-IN LINE3-1 Cb1/B1-IN LINE2-1 Y1/G1-IN LINE1-1 SYNC1-IN SW LINE2 Cr2/R2-IN LINE3-2 Cb2/B2-IN LINE2-2 Y2/G2-IN LINE1-2 SYNC2-IN XTAL DIG Vcc VD1-IN HD1-IN VD2-IN HD2-IN ADDRESS Y-OUT Cb-OUT Vf0ADJ Cr-OUT SYNC3-IN Y3/G3-IN BIAS FIL Cb3/B3-IN Cr3/R3-IN C-IN Y-IN SW LINE1 Symbol V1 V2 V3 V4 V5 V6 V8 V9 V10 V11 V12 V13 V14 V15 V16 V21 V22 V23 V24 V25 V26 V27 V32 V34 V35 V36 V38 V39 V40 V41 V43 V45 V47 V48 Pin open For the TB1308FG only For the TB1308FG only For the TB1308FG only For the TB1308FG only Test Conditions Resistance to 5 V; R = 150 Min 2.6 4.8 2.6 4.8 1.95 4.8 1.4 4.8 2.6 4.8 2.6 4.8 1.95 4.8 1.4 3.7 3.2 1.2 1.2 1.2 1.2 1.8 0.3 1.5 2.2 1.5 1.4 1.95 1.6 2.6 2.6 1.6 1.95 4.8 Typ. 2.7 2.7 2.1 1.75 2.7 2.7 2.1 1.75 3.85 3.35 1.45 1.45 1.45 1.45 2.0 1.0 1.95 2.5 1.95 1.75 2.1 1.8 2.7 2.7 1.7 2.1 Max 2.8 2.8 2.25 2.1 2.8 2.8 2.25 2.1 4.0 3.5 1.7 1.7 1.7 1.7 2.2 1.7 2.4 2.8 2.4 2.1 2.25 2.0 2.8 2.8 1.8 2.25 V Unit
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Video Block
Characteristic Sync-tip clamp mode Input dynamic range Bias mode Chroma input GAIN = 0 I/O gain GAIN = 1 GAIN = 0 GAIN = 1 I/O frequency characteristic 1 GAIN = 0 GAIN = 1 BANDWIDTH = max I/O frequency characteristic 2 BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max I/O frequency characteristic 3 BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max I/O frequency characteristic 4 BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max I/O frequency characteristic 5 Differential 1 of frequency characteristic among 3 outputs Differential 2 of frequency characteristic among 3 outputs Differential 3 of frequency characteristic among 3 outputs I/O delay time 1 BANDWIDTH = cnt BANDWIDTH = min GAIN = 0 GAIN = 1 BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min GAIN = 0 GAIN = 1 BANDWIDTH = max I/O delay time 2 BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max I/O delay time 3 BANDWIDTH = cnt BANDWIDTH = min Symbol Vdsync Vdbias Vdchrm Gfoffg0 Gfoffg6 Gfong0 Gfong6 fg0 fg6 fLmax fLcnt fLmin fHmax fHcnt fHmin fhfLmax fhfLcnt fhfLmin fhfHmax fhfHcnt fhfHmin fdg0 FILPASS = 0, -3 dB point, NOTE 7 fdg6 fdHmax fdHcnt fdHmin fdHmax fdHcnt fdHmin Tdg0 Tdg6 TdLmax TdLcnt TdLmin TdHmax TdHcnt TdHmin FILPASS = 1, GAIN = 0, f0 SW = 1, fc HALF = 1, 1 MHz, NOTE 7 FILPASS = 1, GAIN = 0, f0 SW = 0, 1 MHz, NOTE 7 FILPASS = 1, GAIN = 0, f0 SW = 1, 1 MHz, NOTE 7 FILPASS = 0, 1 MHz, NOTE 7 FILPASS = 1, f0 SW = 0, -3 dB point, NOTE 7 FILPASS = 1, f0 SW = 1, -3 dB point, NOTE 7 -10 -0.90 -0.54 -0.18 -1.30 -1.05 -0.70 18 29 85 10 15 22 35 58 170 0 0 0 0 0 0 0 5 5 23 34 95 15 20 27 40 65 190 10 0.90 0.54 0.18 1.30 1.05 0.70 10 10 28 39 105 20 25 32 45 72 210 ns ns ns ns MHz MHz FILPASS = 1, GAIN = 0, f0 SW = 0, fc HALF = 1, -3 dB point, NOTE 7 FILPASS = 1, GAIN = 0, f0 SW = 1, fc HALF = 1, -3 dB point, NOTE 7 FILPASS = 1, GAIN = 0, f0 SW = 0, -3 dB point, NOTE 7 FILPASS = 1, GAIN = 0, f0 SW = 1, -3 dB point, NOTE 7 Test Conditions FILPASS = 1, BANDWIDTH = max Pin 45 FILPASS = 0, input = 0.2Vp-p 10 kHz FILPASS = 1, f0 SW = 0, BANDWIDTH = min, input = 0.2 Vp-p 10 kHz FILPASS = 0, -3 dB point, NOTE 7 Min 1.40 1.40 1.40 -1.0 5.0 -0.5 5.5 70 60 18.4 11.4 3.7 27.9 21.6 14.6 9.2 5.7 1.85 13.9 10.8 7.3 -10 Typ. 1.65 1.65 1.65 -0.5 5.5 0 6.0 90 80 20.5 12.7 4.2 31.0 24.0 16.3 10.3 6.4 2.1 15.5 12 8.2 0 Max 0 6.0 0.5 6.5 110 100 22.6 14.0 4.7 34.1 26.4 18.0 11.4 7.1 2.35 17.1 13.2 9.1 10 MHz MHz MHz MHz MHz MHz dB Vp-p Unit
BANDWIDTH = max TdhfLmax I/O delay time 4 BANDWIDTH = cnt BANDWIDTH = min TdhfLcnt TdhfLmin
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TB1305FG, TB1308FG
Characteristic Symbol Test Conditions Min 22 FILPASS = 1, GAIN = 0, f0 SW = 0, fc HALF = 1, 1 MHz, NOTE 7 29 45 FILPASS = 0, 1 MHz, NOTE 7 -10 -10 -10 FILPASS = 1, f0 SW = 1, 1 MHz, NOTE 7 -10 -10 0 FILPASS = 1, f0 SW = 0, fc HALF = 1, 1 MHz, NOTE 7 10 35 -10 FILPASS = 1, f0 SW = 0, fc HALF = 1, 1 MHz, NOTE 7 30 MHz sin wave input, NOTE 7 30 MHz sin wave input, NOTE 7 -10 -10 Typ. 27 34 50 0 0 0 0 0 10 20 45 0 0 0 Max 32 39 55 10 10 10 10 10 20 30 55 10 10 10 -50 -50 dB dB ns ns ns ns ns Unit
BANDWIDTH = max TdhfHmax I/O delay time 5 BANDWIDTH = cnt BANDWIDTH = min Differential 1 of delay time among 3 outputs Differential 2 of delay time among 3 outputs Differential 3 of delay time between Y and Cb/Cr outputs Differential 4 of delay time between Cb and Cr outputs GAIN = 0 GAIN = 1 BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min TdhfHcnt TdhfHmin Tddg0 Tddg6 TddHmax TddHcnt TddHmin TddHmax TddHcnt TddHmin TddHmax TddHcnt TddHmin Gmute Gcrs
Mute mode attenuation Crosstalk among inputs
NOTE 7: This parameter is not tested during production and is provided only as information to assist the design of applications.
Synchronization Block (Test condition: A-SYNC = 1 (ON))
Characteristic Symbol VsepL1 525/60i VsepH1 H/V-sync separation level 1125/60i VsepL2 VsepH2 VsepL3 SVGA/60 VsepH3 Threshold amplitude for HD input Threshold amplitude for VD input HD-OUT voltage VthHD VthVDn VhdH VhdL Thdw0 Thdw1 H sync-in to HD-out HD-in to HD-out Thdp1 Thdp2 Test Conditions HV-SEP = 0, 286 mVp-p sync, NOTE 7 HV-SEP = 1, 286 mVp-p sync, NOTE 7 HV-SEP = 0, 0.3 Vp-p sync, NOTE 7 HV-SEP = 1, 0.3 Vp-p sync, NOTE 7 HV-SEP = 0, VGA-SEP = 1, 0.3 Vp-p sync, NOTE 7 HV-SEP = 1, VGA-SEP = 1, 0.3 Vp-p sync, NOTE 7 SYNC SW = 100 SYNC SW = 100 High level Low level HD WIDTH = 0 HD WIDTH = 1 SYNC-SW = 000, 1125/60p input SYNC-SW = 100, NOTE 7 Min 24 27 30 40 14 16 0.8 0.9 3.2 1.55 0.55 130 23 Typ 28 31 34 44 18 20 3.4 0.1 1.65 0.65 150 28 Max 32 % 35 38 48 22 % 24 3.5 0.4 1.75 0.75 170 32 Vp-p Vp-p V % Unit
HD-OUT width
us ns ns
HD-OUT phase
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2007-07-11
TB1305FG, TB1308FG
Characteristic VD-OUT voltage Sync sep 1250i ODD VD-OUT width 1250i EVEN Free-run 1 Free-run 2 Symbol VvdH VvdL Tvdws Tvdwodd Tvdweven Tvdwfi Tvdwfp Tvdp1 Tvdp2 Tvdp3 Tvdp4 Tvdp5 Tvdp6 Tvdp7 V sync-in to VD-out VD-OUT phase Tvdp8 Tvdp9 Tvdp10 Tvdp11 Tvdp12 Tvdp13 Tvdp14 Tvdp15 H sync-in to VD-out VD-in to VD-out Minimum amplitude for suppressed V-sync to separate SYNCOUT voltage HV-SEP = 0 HV-SEP = 1 Tvdp16 Tvdp17 VsupvL VsupvH VsoH VsoL High level Low level Separated VD-OUT When 1250i input Free-run VD-OUT in interlace mode Free-run VD-OUT in progressive mode 625/50i input 525/60i input 625/50p input 525/60p input 1125/50i input 1125/60i input 750/50p input 750/60p input 1125/50p input 1125/60p input VGA/60 input SVGA/60 input XGA input SXGA input UXGA input 1250/50i input, H sync-in to VD-out SYNC-SW=100, NOTE 7 Suppressed H/V-sync input, without picture, NOTE 7 High level Low level Test Conditions Min 3.2 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.10 0.15 0.15 0.15 0.15 0.15 0.15 330 23 3.2 Typ. 3.4 0.1 290 285 270 4 8 0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.15 0.20 0.20 0.20 0.20 0.20 0.20 340 28 3.4 0.1 Max 3.5 0.4 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.26 0.20 0.26 0.26 0.26 0.26 0.26 0.26 350 32 52 48 3.5 0.4 ns ns % H H Unit V us us
V
25
2007-07-11
TB1305FG, TB1308FG
Characteristic Symbol fh156 fh157 fh312 fh315 fh281 fh337 Dummy HD-OUT frequency fh375 fh450 fh1250 fh379 fh640 fh750 fh562 fv625i fv525i fv625p fv525p fv1125i5 fv1125i6 fv750p5 Dummy VD-OUT frequency fv750p6 fv1250iO fv1250iE fvsvga fvsxga fvuxga fv1125p5 VD PHS delay phase others 1125/50p LM MH LH LM MH LH Tvdphs1 Tvdphs2 Vln1LM Vln1MH Vln2LH Vln3LM Vln3MH VlnsLH Zline VdacH VdacL Vontest Test Conditions HV FREQ = 0000, S MODE = 1 HV FREQ = 0001, S MODE = 1 HV FREQ = 0010, S MODE = 1 HV FREQ = 0011, S MODE = 1 HV FREQ = 0100, S MODE = 1 HV FREQ = 0101, S MODE = 1 HV FREQ = 0110, S MODE = 1 HV FREQ = 0111, S MODE = 1 HV FREQ = 1000, S MODE = 1 HV FREQ = 1001, S MODE = 1 HV FREQ = 1010, S MODE = 1 HV FREQ = 1011, S MODE = 1 HV FREQ = 1100, S MODE = 1 HV FREQ = 0000, S MODE = 1 HV FREQ = 0001, S MODE = 1 HV FREQ = 0010, S MODE = 1 HV FREQ = 0011, S MODE = 1 HV FREQ = 0100, S MODE = 1 HV FREQ = 0101, S MODE = 1 HV FREQ = 0110, S MODE = 1 HV FREQ = 0111, S MODE = 1 HV FREQ = 1000, S MODE = 1, ODD HV FREQ = 1000, S MODE = 1, EVEN HV FREQ = 1001, S MODE = 1 HV FREQ = 1010, S MODE = 1 HV FREQ = 1011, S MODE = 1 HV FREQ = 1100, S MODE = 1 No input, S MODE = 1, VD PHS = 1 Min 0.15 0.1 0.8 2.8 0.8 0.8 2.8 0.8 120 4.8 3.6 Typ. 15.564 15.701 31.401 31.401 27.966 33.771 37.288 44.746 31.401 37.288 63.923 74.577 55.932 312.5 262.5 625 525 562.5 562.5 750 750 624.5 625.5 628 1066 1250 1125 0.2 0.15 1.0 3.0 1.0 1.0 3.0 1.0 150 5.0 0.2 Max 0.26 0.2 1.2 3.2 1.2 1.2 3.2 1.2 0.4 k V V V H H kHz Unit
LINE1 detection threshold LINE2 detection threshold LINE3 detection threshold SW LINE detection threshold
Pin 6, 15 Pin 4, 13 Pin 2, 11 Pin 9, 48 Pin 2,4,6,9,11,13,15,48, NOTE 7 High level Low level Pin 45, turned-on voltage for test mode
Input impedance of LINE input pin DAC1,2 output voltage Test mode threshold voltage
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Vcc 5V Q32,Q34,Q36=2SA562TM
Test circuit
L3
38
37
36
35
34
33
32
31
30
29
28
27
26
25
75
Y3-IN 1F CE40
+
C39
R39
39 40 41 42 43
Y3/G3-IN BIAS FIL Cb3/B3-IN DAC2 Cr3/R3-IN
HD1-IN VD1-IN DIG Vcc XTAL DIG GND
24 23 22 21 20
CE24 R24A 1F 100 CE23 R23A 4.7F 100
R24B 75 R23B
HD1-IN
Cb3-IN 1F C41 DAC2-OUT R42 10k C43 1F 1F
75
R41
VD1-IN 0.01F C22 47F
+
75
R22 1/2W 150 X21 CE22 C21 3.579545MHz 10pF
Cr3-IN
R43
75
TB1305FG/TB1308FG
Components in the test circuits are only used to obtain and confirm the device characteristics. These components and circuits do not warrant to prevent the application equipment from malfunction or failure.
44
C45 100pF
+
27
C GND C-IN C Vcc Y-IN SW LINE1
SW1 A B
SCL SDA DAC1 SYNC2-IN LINE1-2
19 18 17 16 15
R19A 470 R18A 470 R17 10k C16 R16 0.1F 1.5k C15 0.1F
SCL
C-IN
R45 CE46 47F L46 0.01F 1F C47 C48 0.1F C46
45 46 47 48
SDA DAC1-OUT
75
Y-IN
R47
75
TB1305FG, TB1308FG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2007-07-11
TB1305FG, TB1308FG
Application circuit 1 (TB1305FG: typical values)
Input video signals, which are driven with low impedance. The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation is required in the mass production design phase. By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
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2007-07-11
Vcc 5V
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Y3-IN 1F
+
39 40 41 42 43
Y3/G3-IN BIAS FIL Cb3/B3-IN DAC2 Cr3/R3-IN
HD1-IN VD1-IN DIG Vcc XTAL DIG GND
24 23 22 21 20
1F
100
HD1-IN
Cb3-IN 1F
4.7F
100 0.01F
VD1-IN
Cr3-IN DAC2-OUT 10k 1F
1/2W 150 47F 10pF 3.579545MHz
+
Input video signals, which are driven with low impedance.
1F
TB1308FG
Application circuit 2 (TB1308FG: typical values)
The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation is required in the mass production design phase. By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
29
44 45 46 47 48
C GND C-IN C Vcc Y-IN SW LINE1
SCL SDA DAC1 SYNC2-IN LINE1-2
19 18 17 16 15
470
SCL
C-IN 100pF
+
470
SDA DAC1-OUT 10k
Y-IN 0.01F 1F
47F
0.1F 1.5k
0.1F
0.1F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TB1305FG, TB1308FG
2007-07-11
INPUT1 (D-pin 1)
INPUT2 (D-pin 2)
TB1305FG, TB1308FG
Application circuit 3 (system configuration)
(1) For non-standard signals such as CVBS, YC (S-video), 525i, 625i or so.
TB1305/08
The TB1305FG and TB1308FG cannot be used for non-standard signals such as weak strength signals, ghost signals and so on. Therefore, these signals should be dealt with through the use of another device such as a color-decoder which is capable of handling these signals. In such cases, the signal switcher and the video circuits of the TB1305FG and TB1308FG can be used. The TB1305FG and TB1308FG cannot distinguish between component and RGB video. The different kinds of input signal should be separated through the use of different signal-specific input pins; for example, specific-purpose pins for RGB video input only or component video input only.
(2) For standard component video (SMPTE STANDARD) and standard RGB video (VESA STANDARD)
TB1305/08
The TB1305FG and TB1308FG can detect a format type for standard signal inputs.
The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation is required in the mass production design phase. By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
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TB1305FG, TB1308FG
Package dimensions
P-QFP48-1014-0.80 Unit: mm
Weight: 0.83 g (typ.)
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Appendix: Comparison Table of the Family
1) Pin functions Pin No. Pin 38 Pin 39 Pin 41 Pin 43 2) Write BUS functions Name YCbCr SW SYNC SW Data 11 010 110 111 TB1305FG Not available Not available HD1/VD1/Not available HD2/VD2/Not available TB1308FG Y3/Cb3/Cr3 SYNC3 HD1/VD1/SYNC3 HD2/VD2/SYNC3 TB1305FG NC NC NC NC TB1308FG SYNC3-IN Y3/G3-IN Cb3/B3-IN Cr3/R3-IN
3) Read BUS functions Name VERSION TB1305FG 00: TB1305FG TB1308FG 01: TB1308FG
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About solderability, following conditions were confirmed * Solderability (1) Use of Sn-37Pb solder Bath * solder bath temperature = 230C * dipping time = 5 seconds * the number of times = once * use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath * solder bath temperature = 245C * dipping time = 5 seconds * the number of times = once * use of R-type flux
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.
*
* The products described in this document are subject to the foreign exchange and foreign trade control laws.
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